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US20050145274A1. Discrete and integrated photo voltaic solar cells. Google Patents

Publication number US20050145274A1 US20050145274A1 US10/958,698 US95869804A US2005145274A1 US 20050145274 A1 US20050145274 A1 US 20050145274A1 US 95869804 A US95869804 A US 95869804A US 2005145274 A1 US2005145274 A1 US 2005145274A1 Authority US United States Prior art keywords substrate cells cell device cell isolation Prior art date 2003-10-03 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.) Granted Application number US10/958,698 Other versions US8334451B2 ( en Inventor Nestore Polce Ronald Clark Nathan Zommer Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.) Littelfuse Inc Original Assignee IXYS LLC Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.) 2003-10-03 Filing date 2004-10-04 Publication date 2005-07-07 Priority claimed from US50835103P external-priority 2004-10-04 Application filed by IXYS LLC filed Critical IXYS LLC 2004-10-04 Priority to US10/958,698 priority Critical patent/US8334451B2/en 2005-03-14 Assigned to IXYS CORPORATION reassignment IXYS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CLARK, RONALD P., POLCE, NESTORE, ZOMMER, NATHAN 2005-07-07 Publication of US20050145274A1 publication Critical patent/US20050145274A1/en 2012-12-18 Application granted granted Critical 2012-12-18 Publication of US8334451B2 publication Critical patent/US8334451B2/en 2018-03-31 Assigned to IXYS, LLC reassignment IXYS, LLC MERGER AND CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: IXYS CORPORATION, IXYS, LLC 2019-05-01 Assigned to LITTELFUSE, INC. reassignment LITTELFUSE, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IXYS, LLC Status Active legal-status Critical Current 2027-11-07 Adjusted expiration legal-status Critical

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H — ELECTRICITY
H01 — ELECTRIC ELEMENTS
H01L — SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L31/00 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H01L31/04 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
H01L31/042 — PV modules or arrays of single PV cells
H01L31/05 — Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
H01L31/0504 — Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
H01L31/0508 — Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module the interconnection means having a particular shape

H — ELECTRICITY
H01 — ELECTRIC ELEMENTS
H01L — SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L31/00 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H01L31/04 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
H01L31/042 — PV modules or arrays of single PV cells
H01L31/0475 — PV cell arrays made by cells in a planar, e.g. repetitive, configuration on a single semiconductor substrate; PV cell microarrays

H — ELECTRICITY
H01 — ELECTRIC ELEMENTS
H01L — SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L31/00 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H01L31/04 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
H01L31/042 — PV modules or arrays of single PV cells
H01L31/048 — Encapsulation of modules

H — ELECTRICITY
H01 — ELECTRIC ELEMENTS
H01L — SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
H01L31/00 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
H01L31/04 — Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
H01L31/042 — PV modules or arrays of single PV cells
H01L31/05 — Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
H01L31/0504 — Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module

Y — GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
Y02 — TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
Y02E — REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
Y02E10/00 — Energy generation through renewable energy sources
Y02E10/50 — Photovoltaic [PV] energy

Abstract

A photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel. The n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions, so that PV cell device is optimized for sunlight.

Description

The present application claims priority from U.S. Provisional Patent Application No. 60/508,351, filed on Oct. 3, 2003, which is incorporated by reference.

State of the art high efficiency photo voltaic (“PV”) solar cells have been introduced as a component in a die (chip) or wafer. A typical solar cell producer uses semiconductor manufacturing processes that are specialized to produce the PV solar cells. The same producer sells the solar cells in the form of chips or wafers. Each solar cell is formed on a single chip or wafer. The buyer of these cells then assembles them in large panels in a series or series-and-parallel combination to produce a higher output power than is possible from one monolithic solar cell.

A solar cell, in its basic form, is a p/n junction (a diode) that generates 0.4-0.7 volts when light shines on it. The high efficiency cells produce the higher voltage range, which is about 0.65v to 0.7v. Accordingly, a user of these cells generally has to connect them in series to generate a higher, more useful voltage. A plurality of such solar cell arrays are connected in parallel to produce higher output current, thereby generating higher electrical power.

For a 6 volt output, 10 PV cells are generally connected in series. Each chip has to be isolated from each other and connected in a scheme, as shown in FIG. 1A. where solar cells PV1 to PV10 are connected in series. The potential of a node 1 is about 6 volts above that of a node 20.

FIG. 1B shows a die bonding and mounting on a substrate 80, where the PV chips are 41-50, representing 10 PV cells, are connected in series. FIG. 1B illustrates a component configuration corresponding to FIG. 1A. The connections are done via conducting wires 61-71. The dice are mounted on conductor pads 21-30. As shown, many additional components (e.g., the connecting wires, conductor pads, and substrate) are needed to place the solar cells in series and obtain a higher voltage output. This results in increased material and labor costs.

One proposed solution has been to use a dielectric isolation (DI) technology. This technology provides a monolithic chip or substrate having a higher voltage output without using connecting wires, conductor pads, and other external components. The DI technology may be used to provide a monolithic substrate having a plurality of solar cells. At first, a photoresist layer is provided on a front side of a silicon substrate. The photoresist is patterned and etched to expose certain parts of the silicon substrate. The exposed parts are etched to form a plurality of grooves on the substrate. The photoresist is then removed.

The substrate is doped with impurities to form a buried layer. An oxide layer is formed on the buried layer. A polysilicon layer is deposited on the oxide layer to a thickness of 500 microns or more. The substrate is then flipped over and grinded to remove excess portions of silicon substrate on the backside.

The DI technology is costly and is generally considered to be impractical. This technology, as explained above, requires deposition of a thick layer of polysilicon and then mechanical coarse grinding techniques, which is both costly and results in a high degree of defects. Also, it is difficult to make a small-sized solar cell devices using the DI technology due to its coarse grinding step.

The present invention relates to a plurality of photo voltaic (PV) solar cells formed on a single or monolithic semiconductor substrate. These PV cells are integrated as a single PV device that outputs a given voltage. The output voltage of the PV device may be customized to a desired level by appropriately connecting a given number of the PV cells in series during fabrication steps of the PV device. Similarly, the output current is also customized to a desired level by appropriately connecting the PV cells in parallel during the fabrication of the PV device. These series and parallel connections are obtained by patterning the interconnect (or metal) layer that is deposited on top of the solar cells.

By using microelectronic techniques disclosed herein, the resultant PV device that outputs a high voltage (e.g., 3 volts) is made much smaller than a conventional device that outputs comparable voltage (see FIG. 1B ). In the present embodiment, a relatively small die sized PV device can be packaged in simple packages, like the ones used in discrete semiconductor devices, e.g., LEDs, transistor diodes etc., with a transparent plastic encapsulation.

As used herein, a packaged device including a PV die is referred to as a “packaged PV device.” The packaged PV device may include one or more PV dice as well as other components. As used herein, a “PV device” generally refers to a die including one or more solar cells. However, PV device may also refer to a packaged PV device, particularly when used in the claims.

In one embodiment, a packaged PV device has a plurality of pins, e.g., two pins, and can be used as a discrete component in a desired circuit or product. Such a discrete product (or a single packaged product) contains one or more small, packaged PV devices with high voltage outputs. Each PV device or die generates about 0.6-0.7 volt of output. The discrete product enables the operation of portable electronic devices with off-line battery chargers, namely using light energy to charge the battery. With the use of such a discrete product, wireless electronic devices or instruments may be mounted virtually anywhere and operated without a fixed power line. These electronic devices can be powered using solar energy using the high efficiency PV devices described herein.

Modem IC’s often requires very low operating or quiescent currents, which the present PV devices can power by charging the battery or energy storage capacitors in the IC’s as part of an electronic device. The present PV device of the present invention may be used in various electronic devices, e.g., remote sensors, which are wireless and free of the need to be connected to a power line. Also, the PV dice themselves can be used as part of batteries to trickle charge the batteries internally if a PV device is implemented as part of the battery. To charge the batteries, a PV device of the desired voltage needs to be selected. For a 1.5 volt batteries, a PV device having 3 PV cells that are integrated to provide about 1.8 volt is needed in the present implementation. The number of PV cells that need to be connected in series depends on the voltage output desired for a PV device.

In one embodiment, a photovoltaic (PV) cell device comprises a first semiconductor substrate; a second semiconductor substrate bonded to the first semiconductor substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of vertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer; a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel. The n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions, so that PV cell device is optimized for sunlight.

Each trench has a width of the opening of that is greater than 5,000 angstroms. Each trench may have a width of at least 2 microns or a width of about 3 microns or more.

In yet another embodiment, a packaged photovoltaic (PV) device includes a PV structure including a silicon-on-silicon (SOI) structure. The PV structure comprises a first silicon semiconductor substrate; a second semiconductor substrate bonded to the first substrate; an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate; a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region; a plurality of trenches provided in the first substrate to separated the PV cells, each trench having a width greater than 1 micron; a plurality of isolation structures provided within the trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel, wherein the n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions. The packaged PV device also includes an electronic component to perform a given function; and a transparent enclosure that encloses both the PV structure and the electronic component.

FIG. 1B illustrates a plurality of PV cells connected in series using a conventional wiring connection method.

FIG. 2A illustrates a cross-sectional view of PV device according to one embodiment of the present invention.

FIG. 2B illustrates a process of forming a PV device according to another embodiment of the present invention.

FIG. 3 illustrates a process of forming a PV device according to one embodiment of the present invention.

FIG. 4A illustrates a monolithic substrate or die defining a plurality of PV cells according to one embodiment of the present invention.

FIG. 4B illustrate a metal layer formed over the substrate of FIG. 4A to obtain 8 volts output according to one embodiment of the present invention.

FIG. 4C illustrate a metal layer formed over the substrate of FIG. 4A to obtain 16 volt output according to one embodiment of the present invention.

FIG. 4D illustrate a metal layer formed over the substrate of FIG. 4A to obtain 2 volt output according to one embodiment of the present invention.

FIG. 4E illustrate a metal layer formed over the substrate of FIG. 4A to obtain 4 volt output according to one embodiment of the present invention.

FIG. 5A illustrates a solar cell module having a lens according to one embodiment of the present invention.

FIG. 5B illustrates a solar cell module having a lens according to another embodiment of the present invention.

FIG. 5C illustrates a solar cell module having a lens according to yet another embodiment of the present invention.

The present invention relates to photo voltaic solar cells. For part of the reasons described above in the background, embodiments of the present invention provide a structure and a method of making a PV chip that can provide a high voltage output by integrating multiple single PV solar cell diodes in one monolithic substrate, e.g., silicon substrate or crystal.

FIG. 2A illustrates a cross-sectional view of a discrete PV device or die 100 according to one embodiment. The PV device 100 is formed using an SOI (Silicon on Insulator) technique to fabricate high efficiency PV cell arrays on a single semiconductor die. The die is packaged as a single discrete device. The PV device includes a first silicon substrate 101 and a second silicon substrate 102. At least one of the two substrates is thermally oxidized to form a silicon dioxide layer 91. The two substrates are bonded together by sandwiching the silicon dioxide layer between them. This creates a bonded structure 200. This structure is also referred to as a wafer bonded structure (WBS) since wafers are generally in the current SOI technology. As well known by those skilled in the art, a plurality of PV devices are defined on the WBS and cut into a plurality of PV devices or dice.

The PV devices are formed on the WBS 200 using semiconductor fabrication techniques (see FIG. 3 ). A photoresist layer is deposited on the upper side of the WBS 200 and patterned to expose certain areas of the first substrate 101 (step 302). The exposed areas are etched to form a plurality of trenches (step 304). These trenches are used to isolate the tubs or active regions whereon the PV solar cells are formed. The trenches are provided with a width of about 3 microns to ensure the isolation between adjacent PV cells. The trench sidewalls are doped to provide internal gettering sites for material defects and impurities (step 306). A silicon dioxide layer is deposited or thermally grown on the trench sidewalls whereon the gettering sites have been formed (step 308). The silicon dioxide layer preferably is at least about 3000 angstroms thick. An undoped polysilicon layer is formed over the silicon dioxide to fill the trenches (step 310). The oxide along is not used to completely fill the trenches since it is relatively high in stress. As the thickness of the oxide deposited on the silicon substrate increases, the stress on the silicon increases as well. For example, an oxide that is greater than about 5000 angstroms in thickness may cause a mechanical failure and damage the crystalline structure of the underlying silicon. That is, a mechanical slip is caused by the high stress resulting from the thick oxide. To present such an occurrence, polysilicon that exerts less stress on the silicon is used in conjunction with the oxide to fill the trenches and act as a insulating material that isolates adjacent tubstub tub.

Referring back to FIG. 2A. the WBS 200 shows a plurality of PV cells (PV1, PV2, and PV3) formed on the first silicon substrate. Isolation structures 92 and 93 electrically isolate the PV cells. The isolation structures includes an oxide layer and undoped poly silicon layer, as described above. Each tub is a diode and includes a p-type region and an n-type region. An interconnect, generally metal, connects the tubs or PV cells in series or parallel according to the desired configuration.

FIG. 2B illustrates a cross-sectional view of a PV device 400 according to another embodiment of the present invention. The PV device 400 includes a plurality of tubs 402, 404, and 406. The tubs are formed on a first silicon substrate 412 that overlies an oxide layer 414. A second silicon substrate (not shown) is provided below the oxide layer. The PV device 400 is made on a wafer bonded structure or SOI structure, as with the PV device 100 of FIG. 2A.

Each tub is a solar cell or PN junction diode that generates electrical current when light is shined thereon or photons are directed toward the surface thereof. The bodies of the tubs are p- type regions 416, 418, and 420. These regions have dopant concentration of about 4 e14 to 7 e14 Boron, and maybe referred to as p- regions. N- type regions 422, 424, and 426 are formed on the upper side of the p-type regions. These have dopant concentration of 5 e19 Arsenic and may be referred to n or emitter regions and can be adjusted both in junction depth and resistivity to be optimized for different wavelengths of light.

For example, in the present embodiment, the n regions are formed using ion implantation of arsenic to provide shallow junction depth of about 1 micron or less. The junction depth preferably should be no more than 2 microns deep to minimize photon recombination therein and provide highly efficient PV cells. The junction depth in question and the tub depth are configured for optimal performance under sunlight and fluorescent light.

A metal interconnect 432 connects the tubs 402, 404, and 406 in series to obtain a high voltage output. The metal interconnect is formed by depositing a metal layer, e.g., aluminum, and then etching it to obtain a desired connection pattern. The metal layer can be patterned to obtain a desired number of tubs in series connection to provide a desired voltage output. Similarly, the metal layer may be patterned to obtain a desired number of tubs in parallel connection to provide a desired level of current output.

The silicon tubs are separated by isolation structures 442 formed within a plurality of trenches. The trenches are vertically (anisotropically) etched in the present embodiment. Sidewalls of the trenches are doped to provide gettering sites 444. A silicon dioxide layer 446 is formed on the gettering sites. Undoped polysilicon is deposited in the trenches and chemically-mechanically polished (CMP) to form polysilicon plugs 448 that are used to fill the trenches.

In addition to the isolation structures 442, the tubs 402, 404, and 406 are electrically isolated from each other by forming them on the oxide layer 414 that has been previously formed to bond the first and second substrates in the SOI technology.

Using the above SOI technology, the resultant die can be scaled up for higher current by incorporating a larger PV diode area for more current output and more PV isolated elements in series for more voltage output. By using silicon substrates that are high quality single crystal silicon, the PV elements produce electrical power at higher efficiency than the DI technology.

Another advantage to the PV device based on SOI technology is derived from utilization of a vertical (anisotropic) etch technology. The resultant vertical trenches enables formation of tubs having a greater 3D volumetric tub area for a given diode size, particularly when compared to a PV device obtained using the DI technology. This is because the DI technology generally uses KOH etching, which is isotropic in nature, to form the trench. As a result sloping sidewalls are obtained.

In one embodiment, an analog or digital control circuits in an integrated form is defined on one of the plurality of PV cell as part of the overall PV device or die. Exemplary functions that can be integrated are: a) voltage regulation circuit, b) current regulation, c) lower voltage lock out (This means that the PV power output is delivered once a certain minimum voltage is achieved; below that voltage, the PV is ‘locked’ out from providing output power), d) protection circuitry to prevent electrostatic discharge damage (ESD protection), or other protection functions.

FIG. 4A illustrates a top view of a partially completed PV device 500 including a plurality of PV cells 502 according to one embodiment of the present invention. The PV device 500 corresponds to the PV device 400 in the present implementation. Adjacent cells are isolated from each other by isolation structures 504. Each cell has one or more contact regions 506. A metal interconnect is patterned to connect these contact regions in a given way to obtain X number of cells in series and Y number of cells in parallel. The number of cells in series is increased if a higher voltage output is desired. Similarly the number of cells in parallel is increased if a higher level of current output is desired. A control circuit 508 is formed at a lower portion of the die. First and second contact pads 510 and 512 are formed to provide electrical connection to an external device.

FIG. 4B illustrates a top view of a metal interconnect 520 that is patterned on top of the partially completed PV device 500 to output about 8 volts according to one embodiment of the present invention. The metal interconnect is aluminum in the present embodiment. The metal interconnect connects the contact regions 506 in such a way that two arrays of 16 cells in series is obtained.

FIG. 4C illustrates a metal interconnection 530 that is patterned on top of the partially completed PV device 500 to output about 16 volts according to one embodiment of the present invention. The metal interconnect connects the contact regions 506 in such a way that an array of 32 cells in series is obtained.

FIG. 4D illustrates a metal interconnection 540 that is patterned on top of the partially completed PV device 500 to output about 16 volts according to one embodiment of the present invention. The metal interconnect connects the contact regions 506 in such a way that eight arrays of 4 cells in series is obtained.

FIG. 4E illustrates a metal interconnection 550 that is patterned on top of the partially completed PV device 500 to output about 16 volts according to one embodiment of the present invention. The metal interconnect connects the contact regions 506 in such a way that four arrays of 8 cells in series is obtained.

FIG. 5A illustrates a packaged PV device 600 having a PV device or die 604 according to one embodiment of the present invention. The packaged PV device 600 includes a plastic or hermetic package with a transparent plastic or glass window 602. The window allows light, represented as arrows 601, to fall on the PV die 604. The die converts the light to electrical power. In particular, FIG. 5A illustrates the use of the PV die in a package for use as an LED. This LED has a dome or lens 603 to FOCUS light onto the die. The electrical power is output through pins 605 and 606 that are coupled to the contact pads (see numeral 510 and 512 of FIG. 4A ) of the die by a wire 607. This method of light concentration increases the power output of the encapsulated integrated PV.

FIG. 5B illustrates a discrete packaged PV device 610 with an integrated concentrating lens 612 and a PV device or die 614 according to another embodiment of the present invention. The electrical power is output through pins 615 and 616 that extends outwardly on the opposite sides of the packaged device. The backside 618 of the package device may be polymer or ceramic materials.

FIG. 5C illustrates a metal-can- hermetic PV device 620 according to yet another embodiment of the present invention. A PV die 621 is mounted inside a metal housing 621. A curved lens 624 concentrates the light onto the die 621. Pins 625 and 626 are used to output the electrical power resulting from the light.

Yet another feature of the invention relates to the assembly of a PV die 632 in an LED package 630 with an LED die 634 adjacent thereto. In many applications for electronic products, it is desirable to have an LED as an indicator lamp or a light source. In some of these applications, it is desirable also to include a PV die to provide electrical charging power. In such applications, a PV die is assembled next to the LED die within the same package of the LED.

This feature uses the LED package for dual purposes. One is to diffuse and spread the LED light out of the package, and another is to concentrate the external incident light into the package and onto the PV die. Furthermore, part of the LED emitted light that is not transmitted out (but is trapped inside the package) is converted back to electrical power by the PV die inside that package. Other combinations of co-packaged LEDs and PV dice can be implemented according to the application needs.

The embodiment described above may be implemented using any of the available LED or optoelectronic packages. A discrete or IC packages may be used in surface mount technology or insertion mount technology, e.g., in SO, or SOT, SIP or DIP standard packages. SO and SOT relate to discrete surface mount packages. SIP refers tot single in line package, and DIP refers to dual in line package.

The present embodiment provides one or more transparent areas above the LED and PV die or dice for multi-chip features.

The present invention has been described in terms of specific embodiment. Accordingly, the present invention may be implemented in other ways.

Claims ( 13 )

an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate;

a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region;

a plurality ofvertical trenches provided in the first substrate to separated the PV cells, the vertical trenches terminating at the insulating layer;

a plurality of isolation structures provided within the vertical trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and

an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel, wherein the n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions, so that PV cell device is optimized for sunlight.

The PV cell device of claim 1. wherein the device is optimized for sunlight or fluorescent light, or both.

The PV cell device of claim 1. wherein the device comprises N number of tubs defined in the first substrate, wherein each PV cell is defined on one of the tubs.

wherein the PV die is configured to power the electronic component using energy generated with the light.

The PV cell device of claim 5. wherein the transparent package includes a curved lens provided above the PV die to direct the light toward the first substrate.

The PV cell device of claim 1. wherein the first and second substrates are bonded to each other and comprise a silicon-on-insulator structure.

The PV cell device of claim 1. wherein each trench having a width of that is greater than 5,000 angstroms.

10. The PV cell device of claim 1. wherein each trench having a width of about 3 microns or more.

an insulating layer provided between the first and second substrates to electrically isolate the first substrate from the second substrate;

a plurality of PV cells defined on the first substrate, each PV cell including a n-type region and a p-type region;

a plurality of trenches provided in the first substrate to separated the PV cells, each trench having a width greater than 1 micron;

a plurality of isolation structures provided within the trenches, each isolation structure including a first isolation layer including oxide and a second isolation layer including polysilicon; and

an interconnect layer patterned to connect the PV cells to provide X number of PV cells in series and Y number of PV cells in parallel,

wherein the n-type regions are formed by performing ion implantation of arsenic to provide shallow junction depths for the n-type regions;

The packaged PV device of claim 11. wherein the transparent enclosure includes a lens to direct light onto the first substrate of the PV structure.

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US20070137700A1 ( en )	2005-12-16	2007-06-21	The Regents Of The University Of California	Development of an electronic device quality aluminum antimonide (AISb) semiconductor for solar cell applications
US20080314439A1 ( en )	2007-06-20	2008-12-25	Misra Mohan S	Array Of Monolithically Integrated Thin Film Photovoltaic Cells And Associated Methods
WO2009038593A1 ( en )	2007-09-20	2009-03-26	Translucent Photonics, Inc.	Thin film solar cell iii
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Elucidating the charge carrier separation and working mechanism of CH3NH3PbI3−xClx perovskite solar cells

Developments in organic–inorganic lead halide-based perovskite solar cells have been meteoric over the last 2 years, with small-area efficiencies surpassing 15%. We address the fundamental issue of how these cells work by applying a scanning electron microscopy-based technique to cell cross-sections. By mapping the variation in efficiency of charge separation and collection in the cross-sections, we show the presence of two prime high efficiency locations, one at/near the absorber/hole-blocking-layer, and the second at/near the absorber/electron-blocking-layer interfaces, with the former more pronounced. This ‘twin-peaks’ profile is characteristic of a p–i–n solar cell, with a layer of low-doped, high electronic quality semiconductor, between a p- and an n-layer. If the electron blocker is replaced by a gold contact, only a heterojunction at the absorber/hole-blocking interface remains.

Introduction

A wide variety of solar cell types exist 1,2. yet in all solar cells the same basic sequence of events occurs: sunlight is absorbed in the cell’s absorber which triggers the generation, separation and transport of electronic charge carriers and their collection at opposing contacts, each selective for one of the carriers 3,4. Cell types differ, however, in how this general flow chart is performed in practice, that is, in the mechanisms that make this sequence of events possible. Elucidating those mechanisms is of fundamental importance for understanding the working principle of each solar cell type, and for its further optimization. This is particularly the case when it comes to the new range of polycrystalline, organic–inorganic lead halide, perovskite cells 5,6. The development of these cells has been Rapid. A stream of reports has come out boasting highly efficient solid-state cells surpassing 15% efficiency 7,8. Most impressive, the CH3NH3PbI3−xClx cells exhibit high VOC values (~1.1 V) 5. reaching qVOC/EGap values of up to 0.71, a remarkably high figure for a new type of cell. In this regard, a central issue that a proposed mechanism needs to be able to explain is the source of the impressive VOC values. When a new star such as the perovskite appears in the solar cell firmament, the first question to naturally arise is: ‘How does it work?’

Here, we elucidate this question by direct measurement of electron beam-induced current (EBIC) profiles of cross-sections of CH3NH3PbI3−xClx-based cells with or without a meso-structured alumina scaffold.

Combining the EBIC signal with the microscope’s scanning capability, an EBIC image results, with the intensity representing the current amplitude generated in the sample. In other words, the EBIC image is a map detailing where in the cell the current is generated and at what degree of efficiency. The intensity of the peaks in the image indicates how efficient the charge separation at, cum collection from, that site in the cell is. The EBIC profile is useful for pinpointing the location of a driving force for charge separation, making it especially suited for determining the working principle of a photovoltaic device. An illustration of the EBIC experiment on a thin film device structure is shown in Fig. 1a. Here we use EBIC to study CH3NH3PbI3−xClx-based photovoltaic devices, and find two peaks in EBIC intensity profile inside the absorber. This shows that the modus operandi of these devices is that of a p–i–n cell with the intrinsic absorber being of high electronic quality material.

Results

Flat device with HTM

Averaged photoelectrical characteristics of devices (with thick mesoporous alumina layer, taken from five devices) are: VOC=0.96 V; JSC=18.5 mA cm −2 ; fill factor=55% and a power conversion efficiency, PCE=9.9% (highest PCE=11%), which show we are in fact investigating state-of-the-art device (Fig. 1b). We note that devices were EBIC-investigated close to their preparation and electrical characterization time. When not investigated, devices were kept in a dark and dry environment and repeated EBIC investigations have shown similar EBIC results, therefore indicating that the cross-sections and devices were stable over the period of interest. Other devices kept in a dark desiccator have also shown stability (in comparison with the initial measurements) for more than a couple of weeks. details about device preparation, EBIC characterization and stability are given in the Methods section. To locate where in the device most of the current is being generated, we measured the EBIC of cross-sections of a number of efficient perovskite solar cell structures. When a scanning beam of electrons, such as used in an electron microscope, is directed towards a semiconductor, it plays an analogous role to that of photons of light, generating free electrons and holes (electron-voltaic versus photovoltaic effect). Because of the high energy of the beam’s incoming electrons, multiple electron-hole pairs are generated (as high energy photons do in the case of so-called multiple exciton generation, but in much larger numbers). If a driving force for charge separation exists in the electron-excited semiconductor and contacts to collect the charge carriers are provided, an electron-voltaic cell is created, and a current is produced in the form of an EBIC signal 9. The electron beam scans the sample, with the volume and depth of charge carrier generation determined by the voltage to which the electrons are accelerated, that is, their energy when they reach the sample surface, and by the sample’s material properties.

In all the cases studied here, the absorber was the perovskite CH3NH3PbI3−xClx as it readily forms larger crystallites than the other halide analogues. In Fig. 2a, a cross-sectional secondary electron (SE) image of a flat cell is shown (that is, without mp-Al2O3; left image), with the corresponding EBIC image on the right. Two line profiles are shown in the bottom panel with the arrows indicating from which region they were taken; the colour-coding corresponds to the different layers that make up the cell. A three-dimensional (3D) surface plot of the EBIC image is shown in Fig. 1b. In the SE image, the different layers of the cell can be distinguished and are (in the direction of the arrows): the 80–100 nm Au (bright), HTM (black), perovskite absorber, 80–100 nm compact TiO2, ca. 700 nm F-doped tin oxide (FTO) on glass. In the EBIC line profiles, we find a ‘two-peak’ pattern, which is dominant throughout the film (regardless of HTM thickness) as can be seen in the 3D surface plot. One peak is at/near the HTM-CH3NH3PbI3−xClx interface and the second peak close to the CH3NH3PbI3−xClx-TiO2 interface, with the peak closer to the HTM being consistently higher. Even though the perovskite film thickness was not uniform throughout the cross-section, an issue already addressed by others 10. the pronounced two-peak pattern extended over the entire length of the cross-section of this cell, except where it is too thin (see below). A non-uniform region in the device showing the transition from a single EBIC peak to a double peak is shown in Supplementary Fig. 1. The ripples on the EBIC scan in the white area to the left of the Au region in the colour-coded line profile are the background noise of the EBIC signal. The stronger EBIC background level on the right side of the sample, which is clearest in the line scans, is due to the insulating nature of the glass.

With an exciton binding energy of up to 50 meV 11. and the excess energy generated by the electron beam, the generated charges in these devices are considered as free electrons and holes. These numbers were recently re-validated by reports from spectroscopic studies that have shown that also under photo-excitation, the vast majority of charges are free electrons and holes 12. Furthermore, the experiment at hand deals with working devices that include (1) the electric fields in the device, (2) the two selective sinks for charge carriers. Both will contribute to free charge carrier population and minimize the exciton population in the measurement at hand (and in the actual working device). Variations in EBIC contrast reflect the dynamics of the carrier lifetime 9,13. The intense signal close to the HTM-CH3NH3PbI3−xClx interface indicates efficient hole extraction. Electrons generated there have to diffuse through the entire width of the absorber layer before being extracted at the TiO2 interface, with increased chances of recombination the further away they are produced from their respective sink. Similar considerations apply to the holes near the TiO2-CH3NH3PbI3−xClx interface. Combining the two decay patterns explains the decrease of the EBIC signal towards the middle of the layer and the formation of a two-peak pattern: each charge carrier is collected at a different end of the cell, forming a distinct decay pattern with its single peak, and the superposition of the hole and electron decay patterns yields a two-peak pattern.

With d representing the absorber width and Ln,p the electron (n) and hole (p) diffusion lengths, the junction pattern observed in the perovskite occurs only if d and Ln,p are comparable (the transition from a single EBIC peak to a double peak can be seen in Supplementary Fig. 1). This two-peak pattern is quite distinct from other junctions. For example, a p–n junction in an absorber forms a single peak, a p–i–n structure with dL reveals two peaks separated by a flat region and a p–i–n structure with dL will have but one peak of width d 14. In a p–i–n device, a near-intrinsic (that is, low-doped) semiconductor film, which acts as solar light absorber, is contacted on both sides with p- and n-semiconductors with different work functions. These semiconductors act as the selective contacting materials. A variety of p–i–n cells exist: in the most common, amorphous Si-based one, the p- and n-semiconductors are the same as the intrinsic one, while in other cells, their materials differ from that of the intrinsic semiconductor (for example, some organic photovoltaic (OPV) cells), and energy-Band offsets may exist at the p–i and i–n junctions. We note that a p–i–n model is among those models previously suggested as possible for CH3NH3PbI3−xClx cells 15. but until now, though, no experimental evidence to support this model (or another) was given. Our results do provide direct experimental evidence of the p–i–n mode of operation of a CH3NH3PbI3−xClx photovoltaic device. That such a model operates in a solution-casted photovoltaic device is made all the more remarkable if we realize that the only p–i–n photovoltaic junction that is comparable with the perovskite photovoltaic junction is based on a structure that requires highly sophisticated preparation methods and high electronic quality absorber, a junction containing AlGaAs/GaAs multiple quantum wells (for comparison, amorphous hydrogenated Si, a-Si:H, has a diffusion length in the range of 0.1–0.2 μm while that of GaAs is ~1–5 μm). The high electronic quality of the absorber material is supported further by recent reports on the high charge mobility and low recombination rates 12,16.

The relative EBIC peak intensities are good indicators of the extraction efficiency of the two charge carriers (at the two selective interfaces). From the EBIC line scans, we calculated effective diffusion lengths, Ln=1.9±0.1 μm and Lp=1.5±0.2 μm (Supplementary Fig. 2) 17,18,19. These values are similar to those calculated recently by Stranks et al. 20 by modelling their time-resolved photoluminescence and absorption experimental data. The peak closer to the HTM was consistently higher than the peak closer to the TiO2, indicating that electrons are extracted more efficiently than holes.

Our EBIC analysis of perovskite cells without an alumina scaffold revealed a two-peak signal shape characteristic of a p–i–n structure with a low-doped active layer between two selective sinks, and d~L. As alluded to above, a similar two-peak pattern is seen in AlGaAs/GaAs multiple quantum well p–i–n solar cells, made by molecular beam epitaxy 21. As we will show later, this p–i–n classification of the perovskite thin-film cells also applies to perovskite cells employing mp-Al2O3 as a scaffold.

First though, we consider the effect of the polycrystalline nature of the perovskite material used, because transport barriers at grain boundaries can affect EBIC analyses and decrease photovoltaic performance. When we analysed the electrostatic landscape of the absorber material using scanning Kelvin probe force microscopy, we detected no significant potential variation across each grain or at its boundary (Supplementary Fig. 3). This finding suggests that the grain boundaries do not contain significant depletion regions and that the electrical current is uniformly photo-generated in the bulk and at the interfaces of the grains, a situation quite different from that of CdTe but somewhat akin to that found for CIGS cells 22,23. This may be the result of a low density of surface states, possibly due to the partial organic nature of this semiconductor, with the organic moieties passivating the surface (amines are well-known passivation agents for II–VI semiconductor surfaces). It is likely that such a low density of surface or interface defects also contributes to the very high VOC values obtained for these cells (because of the absence of pinning at the interfaces).

Devices with a thin mp-Al2O3 and HTM

When we placed a thin (ca. 100–200 nm) mp-Al2O3 layer between the absorber and TiO2, the two-peak pattern remained (Fig. 3), though the signal close to the interface with TiO2 appeared less sharp and the peak seemed to have shifted inward, into the absorber layer. However, we believe it is plausible that the peak shift is due to a concealment effect of the electrons by the mp-Al2O3, which dilutes the current-carrying volume (the alumina does not carry any current from the electro-voltaic effect, but it does absorb some of the electrons from the e-beam), leading to the apparent peak shift.

Devices with a thick mp-Al2O3 and HTM

We also examined a solar cell with a much thicker (ca. 700 nm) mp-alumina scaffold. In Fig. 4, the SE and EBIC images of a cross-section of this cell are shown. From the 3D surface plot of the EBIC image (Fig. 4b), we find there is still a peak in the absorber close to the HTM, more dominant than the peaks we observed close to the HTM before (Figs 2 and 3).

However, the EBIC peak usually located close to the TiO2 interface is now almost entirely obscured by the alumina, although remnants of the signal can still be detected. Furthermore, we note that in areas that do not have a capping layer of absorber on top of the mp-Al2O3, we do not see an EBIC signal (or a very faint one; see Supplementary Fig. 4), implying that this cell does not operate as a nanocomposite, a so-called bulk heterojunction as was speculated before 5. that is to say that the inner mixing of absorber and HTM in the pores are not significant for the functioning of the device per se, and the mixing with mp-Al2O3 likely functions to improve surface coverage. These are indications that the p–i–n model of the cell still holds regardless of the mp-alumina. Furthermore, it suggests that a possible path to improve these cells is to improve the uniformity of the perovskite coverage, a feature that is, to a limited extent, obtained with the alumina scaffold 7,10. In terms of device operation, this inhomogeneity can be visualized as (photo-)diodes with different VOCs connected in parallel, therefore reducing the cell’s overall VOC. The effect on VOC stems from the different dark current that each diode will have 24,25. The local absorber thickness may also affect the local JSC.

Devices with a thin mp-Al2O3 and without HTM

Finally, in Fig. 5, we look at a structure without HTM (a thin mp-Al2O3 was used to prevent shunts from the Au back contact to the TiO2).

Here, we could not detect a two-peak pattern, only a single, broad peak, with its maximum intensity close to the TiO2 and a slow decrease of the signal towards the Au back contact. The absorber thickness in the region between the two arrows is ca. 1 μm, comparable to the thickness of the absorber in Fig. 3 (ca. 1.3 μm at the thin region). The slow decrease in the EBIC signal towards the Au back contact indicates there is no (or very little) Band bending from a Schottky junction at the Au-absorber interface. We therefore conclude that in the absence of a hole-transporting material, the cell functions as a heterojunction between the absorber and the TiO2, with the area of maximum current production and, thus, the position of the junction centre in the perovskite located close to the TiO2. This structure suggests the possibility of increasing the voltage by driving the perovskite into strong inversion.

Discussion

We conclude that these cells, both in the thin film and in the inert mesoporous configuration, operate as a p–i–n device with a high electronic quality.i- layer, and where the quasi-Fermi levels split within this said layer. This is in contrast with other devices, such as p–n junctions where the quasi-Fermi level splitting can take place also outside the space charge region, in the so-called selective contacts. The high VOC arises from having two (half-) junctions in series, each being a separate hetero-junction that contributes to minimize the dark current and maximize the photocurrent, and by their mutual contribution lead to an increased VOC (ref. 26). This is summarized in the schematic Band diagram of a p–n junction (Fig. 6a), an ‘a-Si:H’-like p–i–n junction (Fig. 6b), and our suggested p–i–n Band diagram for CH3NH3PbI3−xClx perovskite-based cells (Fig. 6c), emphasizing the in-homogeneous built-in field in this device in comparison to other p–i–n devices.

The data show that the electron extraction efficiency is somewhat higher than that of holes, and we estimate the effective diffusion lengths for both charge carriers to be greater than 1 μm. Similar to the efficient CIGS cells, the perovskite absorbers are composed of oriented high-quality crystalline grains 5,20 with benign grain boundaries and a low density of surface/interface states. This explains the high efficiency and high qVOC/Egap ratio in the CH3NH3PbI3−xClx perovskite-based cells. In the absence of an HTM, we find little or no field at the perovskite/Au junction and the active junction is then between the perovskite and the TiO2.

Methods

Device fabrication

FTO transparent conducting substrates (Pilkington TEC15) were cut and cleaned by sequential 15 min sonication in warm aqueous alconox solution, deionized water, acetone and ethanol, followed by drying in a N2 stream. A compact ca. 100 nm thin TiO2 was then applied to the clean substrate by spray pyrolysis of 200 mM titanium diisopropoxide bis(acetylacetonate) solution in isopropanol using air as carrier gas on a hot plate set to 350 °C, followed by annealing at 500 °C for 1 h in air.

A mp-Al2O3 scaffold was prepared by spin-coating an alumina nanoparticle paste (d=50 nm) on the compact titania-coated substrates. An alumina nanoparticle suspension in water was used as the basis for the alumina paste. First, the water was replaced by ethanol via repeat separation and re-suspension in ethanol to obtain a 10%wt suspension. Ten grams of this suspension were mixed with 8.33 g of ethyl cellulose solution (5 g of ethanol, 3.33 g α-terpineol, 1 g of 10 cP ethyl cellulose and 1 g of 46 cP ethyl cellulose). The ethanol was removed completely by a rotary evaporator before re-dispersing the paste with ethanol by adding ethanol 2.5 times the weight of the paste. The paste was spin-coated at 500 r.p.m. (4.2 g force) for 5 s, followed by 3,000 r.p.m. (151 g force) for 45 s and then sintered at 550 °C for 2 h to give a ca. 700 nm thin porous film. This basic paste was diluted with ethanol prior to use in a 1:1 weight ratio to form the thin alumina film.

A CH3NH3PbI2Cl solution was prepared as described elsewhere 21. In short, CH3NH3I was prepared by mixing methyl amine (40% in methanol) with hydroiodic acid (57% in water; caution: exothermic reaction) in a 1:1 molar ratio in a 100 ml flask under continuous stirring at 0 °C for 2 h. CH3NH3I was then crystallized by removing the solvent in a rotary evaporator, washing three times in diethyl ether for 30 min and filtering the precipitate. The material, in the form of white crystals, was then dried overnight in vacuum at 60 °C. It was then kept in a dark, dry environment until further use. A 40%wt solution of CH3NH3PbI3−xClx was prepared by mixing PbCl2 and CH3NH3I in a 1:3 molar ratio in N′N-dimethylformamide and heating it to 60 °C until a clear yellow solution was formed. To coat the substrate, the solution was spin-coated in two stages: 5 s at 500 r.p.m. and then at 1,500 r.p.m. (38 g force) for 30 s. The substrate was then heated on a hot plate set at 100 °C for 45 min, after which the substrate turned deep dark brown in colour.

To finish the device fabrication, a 100 μl hole conductor solution (84 mg spiro-MeOTAD in 1 ml chlorobenzene, mixed with 7 μl of tert-butylpyridine and 15 μl of 170 mg/ml LiTFSI, bis(trifluoromethane)sulphonamide, in acetonitrile), was applied by spin-coating 5 s at 500 r.p.m., then at 1,500 r.p.m. for 30 s, and then 100 nm gold contacts were thermally evaporated on the back through a shadow mask with 0.24 cm 2 rectangular holes.

Device characterization

The J–V characteristics were measured with a Keithley 2400-LV SourceMeter and controlled with a Labview-based, in-house designed program. A solar simulator (ScienceTech SF-150) equipped with a 1.5AM filter and calibrated with a Si solar cell IXOLAR High Efficiency SolarBIT (IXYS XOB17-04 × 3) was used for illumination. The devices were characterized through a 0.16 cm 2 mask.

EBIC measurements

After characterizing the devices in the solar simulator, the samples were cleaved by hand after scribing the glass on the back and immediately loaded into the scanning electron microscope vacuum chamber for EBIC measurements. Scanning electron microscope images were taken on a Zeiss SUPRA high-resolution microscope equipped with a Specimen Current Amplifier (GW electronics Inc., Type 31). The gold back contact was connected to the sample holder and, through it, to the preamplifier by a small micromanipulator to enable measuring the sample current. Using the Grün formula, we calculated a penetration depth of ca. 20 nm under working conditions 9 (1.5 keV; working distance of ca. 5 mm and density of the perovskite taken as ca. 4 g ml −1 (ref. 16), suggesting a lateral EBIC resolution of the same order of magnitude. Images were processed using the Fiji package of ImageJ 1.48.

A word of caution: even the relatively low energy, 1.5 keV, electron beam damages the sample over time, with increased exposure. Supplementary Fig. 5 shows the decrease in EBIC intensity with sequential scans. A clear deterioration of the EBIC signal is observed after several acquisition scans.

Additional information

How to cite this article: Edri, E. et al. Elucidating the charge carrier separation and working mechanism of CH3NH3PbI3−xClx perovskite solar cells. Nat. Commun. 5:3461 doi: 10.1038/ncomms4461 (2014).

Acknowledgements

We thank the Leona M. and Harry B. Helmsley Charitable Trust, the Weizmann-UK Joint Research Program, the Israel Ministry of Science’s ‘Tashtiot’ program, Mr Martin Kushner Schnur and the Nancy and Stephen Grand Center for Sensors and Security, for partial support. S.M. thanks PBC Program of the Israel Council for Higher Education for a fellowship. D.C. holds the Sylvia and Rowland Schaefer Chair in Energy research.

Author information

Authors and Affiliations

Department of Materials and Interfaces, Faculty of Chemistry, Weizmann Institute of Science, Rehovot, 76100, Israel Eran Edri, Saar Kirmayer, Sabyasachi Mukhopadhyay, Gary Hodes David Cahen
Department of Chemical Research Support, Faculty of Chemistry, Weizmann Institute of Science, Rehovot, 76100, Israel Konstantin Gartsman

Make a Solar Powered Bug Robot

These robots might be small and somewhat simple minded, but their easy construction, unique locomotion, and quirky personality make them great as a first time robotics project. In this project we will be creating a simple bug-like robot that will store light energy until it has enough power to move itself with a vibration motor. This simple robotics project can be done in a few hours and it is an excellent introduction to the concepts of electronics and soldering.

Step 1: Collect Your Supplies

Below are all of the supplies needed for this project as well as links to buy them. Most of the items you can find on amazon however some of the components are best purchased from Mouser or DigiKey.

Soldering Iron and Solder
Hot Glue
Wire Cutters
Needle Nose Pliers
Jewelry Wire
22AWG Electronics Wire
4700μf capacitor
2.2kΩ resistor
2N3904 NPN Transistor
2N3906 PNP Transistor
Small Solar Cells
Vibration Motor
TC54 Voltage Trigger

Update: It has been brought to my attention that the voltage trigger that I linked to above has become obsolete. But have no fear! I have found what I believe to be a suitable substitute in the DS1233A Voltage Trigger. Unfortunately the legs of this component are different from the TC54 so you’ll have to keep that in mind throughout the project.

Left leg of the TC54 = Middle leg of the DS1233A

Middle leg of the TC54 = Right leg of the DS1233A

Right leg of the TC54 = Left leg of the DS1233A

Step 2: Prepare Your Components

The first part of the Solar Bug Robot that we are going to construct is the solar engine. This is the part of the robot that checks the capacitor to see if it is charged enough. When it is, it dumps all of that power to the motor for a short spurt of movement. To build the Solar Engine first we are going to need to prepare our components. I believe that the easiest way for me to show you this is by referencing the pictures above but I will also write out instructions to narrate what I’m doing.

NOTE: For the sake of consistency when I refer to the left and right legs of the components I am talking about them being oriented with the flat side facing me and the legs pointing down (as shown in most of the pictures.)

First bend the left leg of the 2N3904 to the left and down and the right leg to the right and towards you leaving the middle leg pointing straight down. Now the 2N3906 and the TC54 Voltage Regulator will be bent the same way, with the left and right legs bent outward and down and the middle leg pointing toward you.

Step 3: Connect the 2N3904 to the 2N3906

Time to pull out that soldering iron and and get to work putting this thing together. First place the 2N3904 adjacent to the 2N3906 then solder the middle leg of the 2N3904 to the right leg of the 2N3906.

Next, take the 2.2k resistor and solder it between the right leg of the 2N3904 and the middle leg of the 2N3906. At this point you can use the wire cutters to snip the excess lead from the resistor.

Step 4: Attach the Voltage Trigger

Now let’s throw the voltage trigger into the mix. Solder the left leg of the voltage trigger to the middle leg of the 2N3904 and solder the left leg of the 2N3904 to the right leg of the voltage trigger. At this point your solar engine should look like the first picture above.

Now cut a piece of 22AWG wire about an inch long and solder it between the middle leg of the voltage trigger and the left leg of the 2N3906. Now your solar engine is complete!

Step 5: Attach the Solar Engine to the Capacitor

Note: Now that we have completed the brains of the bot its time to give it a place to store its energy. In this project we will be using an electrolytic capacitor to store electricity. This type of capacitor is what we call polar, this means that it only works in one direction. To figure out which lead is which, look for a stripe printed on the side of the capacitor. This is the negative lead, therefore, the other one is positive. This will be important to this step.

Use a dab of hot glue to attach the solar engine to the capacitor with the negative leg closest to the voltage trigger. Be sure to place it somewhere where the legs of the capacitor will reach.

Now bend the negative leg of the capacitor back and solder it to the right leg of the voltage trigger. Also bend the positive leg of the capacitor into place and solder it to the left leg of the 2N3906.

Step 6: Attach the Motor

Now lets attach the motor! First decide where you want to place the motor, I decided to put the motor coming out the back like a stinger. This requires some planning because the wires on my motor are a bit short. I used the leftover legs that I snipped off of the resistor to extend the motor wires a bit so it would reach the back of my robot.

solder one of the motor wires to the right leg of the 2N3904 and the other wire to the positive end of the capacitor. it doesn’t matter which wire goes where, flipping the wires will just flip the direction of rotation of the motor.

Next use a dab of hot glue to secure the motor in place. Be sure that the counterweight is able to rotate freely or your robot won’t be able to move.

Step 7: Solar Power!!

We are in the home stretch! Now its time to attach the solar panels. First, if there aren’t wires soldered to the panels now is the time to do so. I recommend using two different colors of the 22AWG wire so you can easily identify the positive and negative legs of the solar panel.

Note: In this tutorial I am using two solar panels, however if you only have one that’ll work too. The more panels you have, the faster the capacitor will charge and the more the motor will pulse. So, if you want your bot to move more add more panels.

Use your soldering iron to connect the negative wire of the solar panel to the negative leg of the capacitor. Then, do the same on the other side by connecting the positive end of the panel to positive leg of the capacitor.

Step 8: Make It Look Pretty

At this point your Solar Bug-Bot is almost done! The final step now is just cosmetic.

Cut off two lengths of the jewelry wire about three to four inches long. Use some needle nose pliers to bend either end of both pieces of wire into little feet. Now bend both lengths of wire into an M shape and hot glue them to the bottom of your bot. These will act as the legs of your robot.

And with that your Solar Bug-Bot is complete! Now all you have to do is take them out in the sun and watch them go!

Step 9: How Does It Work?

When the bot enters sunlight the solar panels will begin to charge the capacitor. As it charges the voltage across the capacitor will increase until it eventually surpasses the voltage triggers tipping point. At this point the voltage trigger will apply voltage to the base of the 2N3904. Now because the 2N3904 is an NPN transistor it acts like a switch, when a current is applied to the base it allows current to flow from one side to the other. This switch will activate the motor. The 2N3906, on the other hand, is a PNP transistor. This means it allows current to flow when the base connected to ground. When the 2N3904 is tripped it trips the 2N3906 and completely bypasses the voltage trigger allowing all of the electricity to flow into the motor until the capacitor is empty and ready to be refilled.

Have fun with solar panels for IoT

I’m looking at solar energy to power IoT device that will be used in a car. I did not found a lot of documentation on what we can do with solar panel and what kind of energy we can expect to get with a such system.

This post will summarize the information I got on solar panels and measures done.

Solar panel technology

I uses IXYS panel for my tests as they are the one I was able to find easily with Internet distributors and that look industrial ; I was looking for small one I could mount easily on a PCB. You can also find larger one from china but in my case they did not really fit my need. By-the way if I get some time I’ll test some.

According to this document, the solar panels are based on three technologies :

Polycrystralline – they have a spectral range of 500nm to 1100nm (visible to IR) and a performance of 13%. They are mainly use outdoor.
Monocrystalline – they have a larger spectral sensitivity from 300nm to 1100nm (UV to IR) ; thank to that they have a better efficiency and make sense indoor as outdoor. Performance can reach 22%
Amorphous – the spectral range is 300nm to 600nm (visible) ; they feet well indoor but the efficiency is about 5%

The test I have made are based on a Monocrystalline cell with a 22% efficiency ; the main pain point I’m trying to evaluate is the impact of being behind a windshield in a car where the sun IR are filtered to avoid temperature growth. Meaning that the available spectral width will be limited.

The solar panels are composed of one or more cells, the surface is generally the same for multiple devices, so depending on the cells organization you can choose between a higher voltage capacity or a larger current capacity.

Basically a cell delivers 500mV and 15mA ; depending on package you can have 3 cells (KXOB Series) or 8 cells ( SLMD Series). Cells can be serial or parallel, so this can be something like 3×0.5V = 1.5V with 15mA or 3x15mA = 45mA with 0.5V capability

Then, you can plug multiple modules in parallel or Series to get what you want. Voltage and Current indicated are the one you can expect in the best conditions of sun exposure. Depend on this the result will decrease (really quicky…)

Select the right chip for my test

My first choice was a SLMD600H10-ND (7 unit price) as my need is to power a battery for loading it, this module offers 5.01V/22.3mA in the best situation ; 2 or 3 of these module in parallel could be a good source of energy.

Depending on sun exposure the voltage is varying ; also, depending on the load it will vary, based on U=RI formula.

I’ll do some immediate measure by evaluating the current passing over a 10 ohm resistor and do some long term measure by evaluating current passing over a 2×10 ohm divider bridge and measuring voltage out of this divider with an ADC. The results will be collected, aggregated and transmitted over sigfox network.

I made test with this POW11D2P a 5.5V – 80×100 mono-crystalline solar panel also 3.95 unit price.

Immediate measures

First set of measures have been made a light cloudy day in May in France @ 3:30pm

Inside Car Outside Car SOUTH 2.5mA 5mA NORTH 1.8mA 3.5mA EAST 3mA WEST 3mA EAST-Horizontal 0.7mA 1.4mA WEST-Horizontal 0.9mA 2.2mA

In these test, SOUTH / NORTH / EAST / WEST are in the sky direction, the windshield giving the angle. E/W-Horizontal means that I was using side Windows of the car ; the sensor is in this case not pointing sky.

The car Windows is basically cutting the efficiency of the solar cell by a factor 2 in the tested car. To make a comparison, I did a test in a old C15 vehicle not having thermal windshield, the results are fully different :

Inside Car Outside Car WEST 2.12mA 2.20mA

This factor 2 division have been confirmed with the second mono-crystalline panel (POW111D2P)

Inside Car Outside Car South 52mA 104mA North 19mA 42mA

What have to be noticed is that the cell is able to provide 22mA and that day in the best condition, it provided only 6mA. The previous day when I was calibrating the system, I’ve got some sunny period and got a production up to 20mA. The impact of the weather is really important to be taken into account.

Weather impact on solar energy production

Different solar Panel

I have tested different solar panel offering low cost solution like these one :

1 Mono-crystalline solar panel

This panel is basically a 1 solar panel based on mono-crystalline component. My morning test gave me a 49mA capacity (at 9am) outdoor.

1 Poly-crystalline solar panel

This panel is basically a 1 solar panel based on a poly-crystalline component. My mornin test gave me a 40mA capacity (at 9am) outdoor.

As my test purpose is to use them inside a car, as was interested in the impact on the technology in this case. As poly-crystalline have a larger use of IR it was supposed to be less efficient behind a wind-shield.

outdoor windshield ratio poly-crystalline 43 18 42% mono-crystalline 39 14 36%

This test finally goes at the opposite of what was expected… due to precision of my test it seems that we do not have a real difference between these technologies in term of ratio.

Impact of Temperature

The temperature have a negative impact on the solar panel efficiency. Behind a windshield the temperature can be really high, up to 65°C (you will notice than if like me you try to use a PLA printed box for your device behind the windshield and get a kind of gloubiboulgabox at end of the day) … So according to some website, the impact is about.0,5% per degrees over 25°C. It means for 65°C, the impact can be about 20%

Quality of 1 solar panel

The price is one thing but the quality is another. I received different lot of solar panel with different visible quality for China. I can confirm it is better to verify panels are working correctly as on a lot of 55 I have been tested 3 were not working (5%).

During this test, I measured the shortcut current on a constant light for each of the panels. The result is shown in the above graphic showing the number of panel delivering the current slot (23,5 means delivering between 23 24mAh) :

The performance variation is up to 12% for a working panel to another. The average is 24,5 in the test conditions.

Mounting solar panel

Parallel solution

The first way to power my circuit was to use an existing solution based on a LiPo charger circuit MCP73831T. This circuit is requiring 2,7 to 5.5 volt as input. The best way was to connect two solar panel in parallel to get more energy from them.

To get a higher current, it is possible to mount two (or more) solar panel in parallel; to protect them against current fall-back from circuit when solar panel goes to the dark, a diode is added in series ; to avoid current peak over a limit accepted by the circuit next to the panel, a Zener diode is added like in the above schema.

This solution is not efficient enough, my measure gave me bad results as getting only 8mAh going to the battery by a sunny day at noon being right in front of sun… This decreasing to 5.5mAh once the windshield temperature grown. There are different reason for this :

MCP73831 is a linear regulator, not efficient to transform the solar energy to refill the battery
MCP73831 is not designed for solar panel and is not able to adapt its impedance to optimize the solar panel
When I did the measure I do not exactly know what was the battery state but charge current depends on battery charge level – by the way 10mA is not a normal charing level for something like 50% charged.

After looking ate the Serial Solution described above, I did a try with a Texas Instrument BQ25504 ultra low power boost for energy harvester application. This chip implements a MPPT system to optimize solar harvesting.

Serial solution

The second solution was so to use a specific solar panel charger like sparkfun sunny buddy based on a LT3652 device. This device requiers move than 5v as a power supply to be efficient. For this reason the solar panel mounting will be serial :

solar cell serial circuit

This circuit have 3 diodes, the one on top is a blocking diode to protect energy loss in the panels when in the night. The two other are bypass diode : if one of the panel is in the shadow, the second one will be able to produce something the power level will be lower (only one panel). For a use with LT3652, we do not really need them as with 5V the circuit is not working.

Be careful when connecting the battery to the sunny buddy, mine was reversed. Ground here is on the top as for the other load connector.

I made a small change : removing the Timer pin capacitor : this is stopping battery charging after about 4 hours. So I replaced C6 by a 0 ohm resistor as indicated in the documentation to stop charging when C/10. This mean, the charging is finished when the overall load is Isense / 10.

By default Isense = 450mA so C/10 is too high. As my battery is 300mAh, default value is too high and as the maximum current I can get from the solar panel I’m using is 50mAh all of this is really too high. So, I also changed Rsense to have a 150mA Isense.

Rsense = 0.1 / Isense = 0.1 / 0.15 = 0.66 ohm

With this solution, here are the results I got

Cloudy summer day Blue sky summer day peak current produced in the car 20mAh 50mAh

This sounds really nice but in the real world it did not gave me the expected result: the LT3652 have a boost mechanism to extract the maximum power of the solar panel even with a small luminosity as a consequence it consumes battery energy for this. The matter it consumes about 10mA even if the load does not need this. And basically the battery is discharging more than it is charging if the solar exposition is not good. This solution was not the good one for my application with a small solar panel. I recommend to test it if you have large 12V solar panel with a good and constant exposure.

Long term measures

In this test, the sensor is put in a car and we don’t care about the sensor when driving and parking the car to get something like a real use case, even if not especially representative.

The first thing noticed is that energy is produce ( 1mA) from 8am to 5-7pm not more in a light-cloudy day. This is 9-11 hours of production only in good weather condition to refuel a battery.

On a sunny day where I got about 40mAh per cell cumulated during the day. A dark rainy day has given about 12mAh cumulated the day.

As an example, here is the energy captured during a winter period on a week from 2 solar cells :

We have large variation depending on weather and for sure exposing time.

—- Will be completed soon when data will be gathered —

Sources:

https://www.google.sr/patents/US20050145274
https://www.nature.com/articles/ncomms4461
https://www.instructables.com/Make-a-Solar-Powered-Bug-Robot/?amp_page=true
https://www.disk91.com/2015/technology/hardware/have-fun-with-solar-panels-for-iot/

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Elucidating the charge carrier separation and working mechanism of CH3NH3PbI3−xClx…

US20050145274A1. Discrete and integrated photo voltaic solar cells. Google Patents

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Elucidating the charge carrier separation and working mechanism of CH3NH3PbI3−xClx perovskite solar cells

Introduction

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Flat device with HTM

Devices with a thin mp-Al2O3 and HTM

Devices with a thick mp-Al2O3 and HTM

Devices with a thin mp-Al2O3 and without HTM

Discussion

Methods

Device fabrication

Device characterization

EBIC measurements

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Make a Solar Powered Bug Robot

Step 1: Collect Your Supplies

Step 2: Prepare Your Components

Step 3: Connect the 2N3904 to the 2N3906

Step 4: Attach the Voltage Trigger

Step 5: Attach the Solar Engine to the Capacitor

Step 6: Attach the Motor

Step 7: Solar Power!!

Step 8: Make It Look Pretty

Step 9: How Does It Work?

Have fun with solar panels for IoT

Solar panel technology

Select the right chip for my test

Immediate measures

Different solar Panel

Impact of Temperature

Quality of 1 solar panel

Mounting solar panel

Parallel solution

Serial solution

Long term measures

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